The present invention relates to a semiconductor memory system and a controlling method thereof, and more particularly, to a semiconductor memory system having an ECC circuit and a controlling method thereof.
In recent semiconductor memory systems using NAND flash memories, when data is written to memory cells, threshold levels of the memory cells having stored data are frequently varied by malfunction or influence of adjacent cells on which a write operation is performed. The variation in the threshold levels degrades the accuracy of read data. In order to enhance the accuracy of data, error-correcting code (hereinafter, referred to as ECC) is added to data, and then a write operation and a read operation are performed.
Typically, semiconductor memory systems having ECC circuits generate and store parity bits as well as data bits, determine whether errors occur or not by using the parity bits, and correct the errors.
Meanwhile, when errors outside of a correctable range occur, the ECC circuits may correct errors and output corrected data, while not recognizing the situation. Hence, when errors are out of an error correction range, the ECC circuits may correct errors of read data incorrectly. For example, the occurrence of multiple bit errors caused by power failure during the operation of a semiconductor memory system is a situation that exceeds the error correction range. However, in this case, when data is corrected using the ECC circuit, the ECC circuit may determine the errors not as resulting from a power failure, but as defects of memory cells, that is, a read operation failure. Consequently, there is a need for methods that determine whether errors exceed the error correction range of the ECC circuit.